Computer Architecture & Systems
⏱ ~3-min readAceMark Guide
What this topic is really about
Paging in virtual memory management allows processes to use more memory than physically available by dividing memory into fixed-size pages.. Paging divides logical and physical memory into fixed-size pages so non-contiguous physical frames can back a process and parts can be swapped to disk, letting programs use more memory than is physically installed.
A cache speeds up memory access by holding frequently accessed data closer to the CPU with faster access time.. A cache exploits locality of reference by keeping recently and frequently used data in very fast memory close to the processor, reducing average access time.
See the mechanism
During each fetch‑decode‑execute cycle the PC provides the memory address of the upcoming instruction and is then incremented so that execution proceeds sequentially. A diagram for this topic isn't available yet — the worked example below walks the same reasoning step by step.
An exam-style question, fully explained
In the fetch-decode-execute cycle, which register holds the address of the next instruction to be fetched?
- Identify what the question tests: In the fetch-decode-execute cycle, which register holds the address of the next instruction to be fetched.
- The program counter holds the memory address of the next instruction and is incremented during each cycle so execution proceeds in sequence.
- The current instruction register is tempting but stores the instruction currently being decoded, not the address of the next one.
- Why it matters: During each fetch‑decode‑execute cycle the PC provides the memory address of the upcoming instruction and is then incremented so that execution proceeds sequentially. The Current Instruction Register stores the fetched instruction itself, not its address.
Traps the examiner sets
- Students often confuse the PC with the Current Instruction Register, thinking the latter holds the address rather than the actual instruction code.
- Many people confuse RISC with CISC, thinking that RISC processors have a larger and more complex instruction set, when in fact it is the opposite. This confusion can lead to misunderstandings about the design philosophy and advantages of RISC processors.
- Some people mistakenly believe that a cache increases the total RAM capacity, but this is incorrect because the cache is small and supplements rather than expands main memory. Others may think that a cache permanently stores all program data, which is also incorrect because the cache only stores frequently accessed data.
- Some may confuse paging with encryption or increasing CPU clock speed, but paging is primarily concerned with managing memory allocation and swapping pages to disk for efficient use.
- The current instruction register is tempting but stores the instruction currently being decoded, not the address of the next one.
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